17 General receiver architectural functionality.
3G AND BEYOND DISCUSSION 497
To/From
RF
To/From
AP
RF Codecs
(ADC/DAC)
MCU
RF Control
Power
Management
Memory (I/D)
Memory (I/D)
DSP
Dedicated HW
Accelerators
Audio
Codec
I/Os
I/Os
Memory
Cache
Cache
FIGURE 9.18 Communications processor functionality.
SIO Memory (I/D)
MCU
Display
Drivers
Power
Management
I/O
Memory
Graphics HW
Accelerators
Audio
Codec
Memory
I/O
Memory
Digital
TV
Keypad
Control
Camera &
Video
Processing
Java HW
Accelerators
BT, WLAN,GPS, IrDA, FM Radio, etc.
Data I/O
To/From
CP
To/From
Multimedia I/O
Cache
FIGURE 9.19 Applications processor functionality.
498 CHAPTER NINE
FIGURE 9.20 Overall transceiver block diagram emphasizing computational bottlenecks.
RF
Rx
Tx
RAKE
Closed Loop Processing
Spreading
TrCh
Demux
TrCh
Mux
Searchers
MCU
Memory
Interface
Multimedia
(Video, etc.)
Vocoders Speakers
/Mics
MCU
Memory
Another Layer 1
BT, WLAN, GPS, etc.
Display/Camera
Memory
Interface
= Areas of Concern
The block diagram includes the display(s) drivers and keypad control. As mentioned above,
quite a few UE manufacturers produce terminals with two cameras. As time progresses the camera
resolution, measured in megapixels, increases.
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