In the block diagram in Fig. 7.83, we have assumed
to be tracking the CPICH physical channel. In this case, we can improve noise immunity by integrating
longer; however, we would be susceptible to degradation due to larger frequency offsets and timevarying
channels.
The RAKE finger block diagram in Fig. 7.83 essentially has two sections: time tracking and data
demodulation. The upper part consists of the time-tracking functions while the lower part shows the
data-despreading/demodulating functions.
A tremendous amount of literature exists about the analysis of the DLL; we refer them to the interested
reader [4, 24, 31, 32]. However, we will provide the baseline mathematical description for illustrative
purposes. We assume the received signal encountered a flat fading channel with time delay t.
In the case of a frequency-selective fading channel, each of the distinct arriving multipaths will have
3G WIDEBAND CDMA 409
FIGURE 7.81 Optimal chip-time sampling example.
On time
Late Early
0 Tc ??“Tc 2Tc ??“2Tc
FIGURE 7.82 Chip-timing offset example.
On time
Late
Early
0 ??“2Tc 2Tc ??“Tc Tc
a DLL tracking them individually. In this case, there will be autocorrelation contributions among all
the paths. The received signal is given as
(7.
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