A previous solution was to add an equalizer
at the RAKE output to decrease the detrimental effects of ISI. A simplified block diagram is
shown in Fig. 7.77.
3G WIDEBAND CDMA 407
FIGURE 7.78 RAKE finger architecture based on symbol level buffering.
X
X
CCCH
X
CDCH
Finger
Input *
Buffering
MA
Finger
Output
Chips Symbols
CCH
??‘
SF
??‘
FIGURE 7.77 Modified RAKE receiver block diagram.
X X
+
S(t ??“ t1)
w1(t) = h1(t)
X X
S(t ??“ tN)
wN(t) = hN(t)
.
.
.
.
.
.
RAKE
Input
y(t)
Equalizer
yo(t)
(Adaptive)
t1+PG
t1
dt ??«
tN+PG
tN
dt ??«
*
*
At the RAKE output, there are certain bit fields (i.e., pilot bits) that can be used to train the equalizer.
Also a RAKE, actively demodulating a few multipaths has an output symbol sequence that can be reliably
used in a decision-directed mode to update the equalizer taps for the time-varying channel conditions. On
the downlink, dedicated pilot bits and the CPICH are also present to aid in the equalizer weight update.
RAKE Finger Memory Requirements. In this section, we will discuss the memory requirements
to support CE used for coherent demodulation. As shown earlier, on the uplink, the dedicated pilot
bits are time multiplexed within a time slot.
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