41a)
(7.41b)
(7.42)
After careful inspection of the tabulated PN contents (provided earlier in Fig. 7.25), we notice this
corresponds to a shift of 6 chips at the output.
The second approach we will discuss is called masking. Let us consider the block diagram
redrawn in Fig. 7.27 with the mathematical expressions for the PN output and delayed PN output
sequences.
a(x) 10011101001c
a(x) 1 x3 x4 x5 x7 x10 c
a(x)
d(x)
p(x)
1 x
1 x x3
d(x) 1 x
d(x) [1 # (1 x x3)]Degree 3
d(x) [1 # p(x)]Degree 3
3G WIDEBAND CDMA 363
FIGURE 7.27 Masking technique applied to the PN sequence generator.
a2 a1
+
PN Output
a0
X m0 X m1 X m2
+ Delayed
PN Output Mask
d(x)
p(x)
m(x)
p(x)
a(x) =
Using the above definitions, we have the following variables:
(7.43)
d(x) x2
m(x) [110] 1 x
a(x) [100] x2
p(x) 1 x x3
Note that in Fig. 7.27, the PN output and delayed PN output sequences can be derived by division
of two polynomials. In the top case, the PN sequence is delayed by the initial contents of the shift registers,
which is used to generate the d(x) polynomial. The bottom case can delay the output PN
sequence by dividing the mask polynomial by the code polynomial.
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