Below we present an
AFC technique applied to the /4-DQPSK, which can be extended to other modulation schemes. We
will also provide approximations to the error estimator. The first technique will be called AFC-One
and is shown in Fig. 6.43.
In the above AFC algorithm we have made use of the differential detector. The differential detector??™s
phase is denoted as 2 and the quantized symbols phase is denoted as 1. This was accomplished
through the help of an ATAN function which can be implemented with Taylor series expansions or
LUT. The error signal, e(t), is obtained by the difference of the two estimated phases. The estimated
error signal enters the loop filter and then goes to the VCO. The design of the loop filter is important
since it will define the loop noise bandwidth, control convergence time, and affect system
performance.
v
1
T
# ATANadQ(t)
dI(t) b v
1
T
# arg5Rh(T)6
E5d(t)6 Rh(T) s2h
# Jo(vdT) # ejvT
d(t) h(t) # h*(t T) # ej[f(t)vT ]
332 CHAPTER SIX
Differential
Detector
X
e j( )
Ts
+ LPF
RI(t) + jRQ(t) Quantizer
??“
Phase
Detector
Low-Pass
Filtering
VCO
FIGURE 6.42 /4-DQPSK frequency estimation and compensation block diagram.
The corresponding error signal for this AFC-One algorithm can be written as
(6.
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