27 Maximum likelihood timing error estimator.
0 T tj
FIGURE 6.28 Oversampled
symbol diagram.
3 In a section that follows, we plot the performance as a function of timing offset. The system designer will allocate a certain
amount of degradation allowed in order to meet the overall required performance link budget.
RECEIVER DIGITAL SIGNAL PROCESSING 323
Slightly Oversampled
Memory
r(k)
a(kT)
Decision
Device
Memory
Compute Likelihood
Choose
Max
ADC
~
r(t)
Sampling
Clock, fs
tj
Terminate
Interpolation
Control
Interp Interp
No
Yes
t???
FIGURE 6.29 An iterative ML-based timing recovery method using a free-running clock.
0 0 T 0 T
B0 B0 A0
A1
B1
A1
A2
B2
T
t = 2 t = 1 t = 0
FIGURE 6.30 Eye diagram representation at each iteration of the
ML-based timing recovery method.
We will discuss this alternative technique in the context of iterative timing-error estimation. Here
the available samples are first tested against the ML criteria. After this test, one timing instance is chosen
and we interpolate to either side of the temporary estimate to provide new timing offset error candidates.
Each of these new samples are tested against the ML criteria and upon selection of a new
temporary estimate, two newer samples are interpolated on either side and this iterative procedure
repeats until a certain criteria is met.
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