A block diagram of the DFE equalizer is shown in Fig. 6.3. Using our nomenclature the example
structure is called DFE (3, 1). We have chosen to emphasize the FFF with a fractionally spaced structure
and the FBF with a symbol spaced structure. As shown in the equalizer outline chart, this type of
equalizer is nonlinear in that it contains a feedback component originating from the detector (or decisions
device) output.
Bidirectional Equalization. In this section, we will provide some general insight into the training
mode of equalization. For time division multiple access (TDMA) systems, a synchronization word is
transmitted for a number of reasons??”one use is to train the equalizer. Similarly, CDMA systems
transmit not only dedicated pilot bits but also pilot channels which serve the same purpose. Since pilot
channels are continuously transmitted, the equalizer can essentially be placed into training mode. For
sake of this discussion let??™s assume the following time slot structure (see Fig. 6.4).
The typical procedure is to use a priori information such as pilot bits to train the equalizer and then
switch into decision directed mode. The next time slot boundary the mode is switched back into
training mode and this procedure starts over again.
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