Let us consider a 3.2-kbps binary FSK modem using an FEC code. Our objective is to protect our
information against a 10-msec burst of errors. So in designing the interleaver we proceed as follows.
The bit time duration is defined as
(5.1)
Our protection depth or interleaver depth becomes
(5.2)
Hence we would propose using a 32 M size block interleaving scheme. The value of M will be
discussed more in the following sections of this chapter, since this is related to the error correction
capability of the FEC code. A last point to make here is that the combined delay of the interleaver and
de-interleaver is not considered to be a variable that should be minimized in this example.
Depth
10 msec
0.132 msec 33 bits
Tb
1
Rb
1
3.2 kbps 0.312 msec
Convolutional Type. The convolutional interleaving operation consists of B parallel delay elements
(e.g., FIFOs). As a new bit to be transmitted in inserted, the switch moves to the next element to be
used. An example of such an interleaver is shown in Fig. 5.8 [3].
PERFORMANCE IMPROVEMENT TECHNIQUES 229
FEC
Encoder
i
i
2i
i + 1 (B??“1)i
...
...
To
Modulator
FIGURE 5.8 Convolutional interleaving block diagram.
The interleaver??™s switches move from one position to the next as new bits are introduced to the
block.
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