However, the benefits of using this randomizing approach can be
226 CHAPTER FIVE
FEC
Encoder Interleaver Modulator
FEC
Decoder
Deinterleaver
Demodulator
C
H
A
N
N
E
L
Ru (Bps) Rc (Bps) Rc (Bps)
Rs (Sps)
Transmit
Bits
Receive
Bits
FIGURE 5.1 Coded communication system block diagram.
FEC
Decoder
Deinterleaver
Demodulator
Bursty
Errors
Random
Errors
Ru (Bps) Rc (Bps) Rc (Bps) Rs (Sps)
Error-
Corrected
Bits
FIGURE 5.2 Coded communication system receive block diagram.
tremendous. The worse case time delay when considering both the interleaving and de-interleaving
operations is given by 2NM bits.
Let us consider the following bursty error example (see Fig. 5.5). The transmitted bit stream consists
of concatenated columns as shown below (Cij ith column and jth row element).
PERFORMANCE IMPROVEMENT TECHNIQUES 227
Data Input
in Rows.
Data Output
in Columns.
M Columns
N Rows ..
.
. . .
FIGURE 5.3 Block interleaver example.
Data Output
in Rows.
Data Input
into Columns.
M Columns
N Rows ..
.
. . .
FIGURE 5.4 Block de-interleaver example.
CM1 CM2 . . . CMN
CM1 CM2 . . . CMN
C11 C12 . . . C1N
X11 X12 . . . X1N
C21 C22 . . . C2N
C21 C22 . . . C2N
Transmitted Bits
Channel
Response Burst of Errors
Received Bits
X = error
FIGURE 5.
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