A similar receiver block diagram is shown in Fig. 4.8 for DQPSK modulation, where it also provides
an example of generating the 1/2 symbol clock.
Above the received signal is quadrupled and multiplied by a half symbol clock to generate a signal
centered at 4x??™s the carrier frequency. The carrier x??™s 4 signal is extracted by a BPF and then
divided by 4 to obtain the carrier frequency prior to entering the quadrature demodulator. Note a limiter
can be inserted into this signal path to help remove the effects of amplitude modulation/variation.
Also the correct estimate of the time delay through the BPF and dividing circuits is critical for best
system performance. The delay block is used to time align the received signal with the estimated
coherent reference signal.
Now let??™s actually follow the signal path as it passes through this receiver. After the quadrupler we
have the following mathematical representation
(4.24)
Since we have modeled the p/4-DQPSK modulation as 4-level FM, let us concentrate on the signal
centered at 4x??™s the carrier frequency.
(4.25)
(4.26)
(4.27) so(t) K(t) # cos c4vct
a(t) # p
Ts d
so(t) K(t) # cos c4vct 4 # a(t) # 2p # 1
8Ts d so(t) K(t) # cos[4vct 4u(t)]
s4(t)
1
4
# A4(t) # e1 2 # cos[2vct 2u(t)]
1
2
1
2
# cos[4vct 4u(t)] f
MODULATION DETECTION TECHNIQUES 179
BPF
BPF
Half-Symbol
Clock
( )2 LNA
r(t)
Limiter ?· 2
Delay
Quad
Demod
I(t)
Q(t)
FIGURE 4.
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