1.30). Using Eq. (1.9) for the generation of the complex-valued PN code sequence, but with
different encoding rules, we simply group the incoming bits into groups of 8 bits and use those 8 bits
to calculate a CCK chip sequence of length 8.
5ej(f1f2f3f4), ej(f1f3f4), ej(f1f2f4), ej(f1f4), ej(f1f2f3), ej(f1f3), ej(f1f2), ejf16
51,1,1,1,1,1,1,1,1,1,16
WIRELESS TOPICS 23
DBPSK
Modulator
Spread
by 11 Chips
1 Mbps 1 Mbps
1 ?— 11
= 11 Mcps
DQPSK
Modulator
Spread
by 11 Chips
2 Mbps 1 Msps
1 ?— 11
= 11 Mcps
FIGURE 1.27 A 1-Mbps DBPSK transmission block diagram.
FIGURE 1.28 A 2-Mbps DQPSK transmission block diagram.
Some general system characteristics are a transmit frequency tolerance of less than or equal to
25 ppm, and an Error Vector Magnitude (EVM) requirement of less than 35%, utilizing a 25-MHz
channel spacing, output power less than 1 W, and so forth.
In addition to the DSSS physical layer mentioned above, there is a Frequency Hopping Spread
Spectrum (FHSS) physical layer as well. The data rates supported are from 1 to 4.5 Mbps in increments
of 0.5 Mbps. The FHSS PPDU structure is shown in Fig. 1.31.
24 CHAPTER ONE
Group
4 Bits
Spread
by 8 Chips
5.5 Mbps
5.5/4
Mbps
(5.
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